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HY-DDR3 / H5TC4G43AFR-PBA

  • VDD=VDDQ=1.35V + 0.100 / - 0.067V
  • Fully differential clock inputs (CK, /CK) operation
  • Differential Data Strobe (DQS, /DQS)
  • On chip DLL align DQ, DQS and /DQS transition with CK transition
  • DM masks write data-in at the both rising and falling edges of the data strobe
  • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
  • Programmable CAS latency 6, 7, 8, 9, 10 and 11, 13 supported
  • Programmable additive latency 0, CL-1, and CL-2 supported
  • Programmable CAS Write latency (CWL) = 5, 6, 7, 8
  • Programmable burst length 4/8 with both nibble sequential and interleave mode
  • BL switch on the fly
  • 8banks
  • Average Refresh Cycle(Tcase of 0oC~ 95oC)
    - 7.8 μs at 0oC ~ 85oC
    - 3.9 μs at 85oC ~ 95oC
    Commercial Temperature( 0oC ~ 95oC)
    Industrial Temperature( -45oC ~ 95 oC)
  • Auto Self Refresh supported
  • JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16)Driver strength selected by EMRS
  • Dynamic On Die Termination supported
  • Asynchronous RESET pin supported
  • ZQ calibration supported
  • TDQS (Termination Data Strobe) supported (x8 only)
  • Write Levelization supported
  • 8 bit pre-fetch
    • Mobile CPU
    • CPU recovery
    • Other Chips

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